The present invention relates generally to display devices and, more particularly, to a display device of the so-called panel type having a plurality of picture elements or “pixels” which are disposed on a substrate in a matrix form and more than one drive circuit chip for driving these pixels.
Light weight and slim size of display devices of the panel type are presently used as display devices for personal computers (PCs) and handheld or “mobile” wireless telephone handsets plus mobile electronic information terminals such as personal digital assistant (PDA) tools and also as monitors of a variety of types of information equipment. Currently known examples of such panel-type display devices include liquid crystal display (LCD) panels, electro-luminescence (EL) panels, plasma panels, and field emission display (FED) devices with more than one carbon nano-tube (CNT) or the like as the electron source thereof.
A typical one of the panel-type display devices of this type is designed so that a plurality of pixels are disposed in the form of a matrix at a gape space between a pair of spatially adhered substrates to thereby provide a display region while mounting drive circuitry for driving the pixels outside of the display region. The pixels which are laid out in the matrix form are disposed at cross points or “intersections” between a group of parallel drive lines extending in one direction of a substrate surface and a group of drive lines extending in another direction crossing this direction, respectively. Although various pixel design methods are presently available, one approach is to employ a simple matrix scheme which utilizes voltage superposition at an intersection between the both drive lines. Another approach is to use an active matrix scheme which performs selection on a per-pixel basis to turn on.
In recent years, the active matrix scheme for performing selection in units of pixels to turn on is accepted among those skilled in the art as the major approach from viewpoints of enhanced performances, such as image resolutions, contrasts and operation speeds. In display devices of any scheme also, more than one drive circuit is provided outside of the display region in order to supply a drive voltage or display signal to a respective one of the drive lines. Typically this type of drive circuit is provided in the form of a semiconductor chip (referred to as “drive circuit chip” hereinafter) on a substrate or alternatively at the periphery of such substrate.
A typical liquid crystal display device of the type using the active matrix scheme is arranged to have a pair of substrates spatially bonded together with a layer of liquid crystal material filled in a thin gap space therebetween, wherein one substrate has its inner surface on which switching elements for pixel selection use and scan lines for applying a scan voltage(s) to the switching elements along with data lines for display data application and pixel electrodes or the like are formed whereas the other substrate comes with opposite or “counter” electrodes opposing the pixel electrodes or a color filter(s) or the like as formed thereon. Here, letting a widely used liquid crystal display device with thin-film transistors (TFTs) as the switching elements be an example, an arrangement of its drive circuit chip will be explained below. Due to this, an explanation will be given under an assumption that the scan lines for scan voltage application are regarded as gate lines whereas the data lines for display data application are drain lines.
FIG. 7 is a diagram showing a pictorial representation for explanation of an arrangement of a ventral surface (parts-mount face) of a gate drive circuit chip which applies a drive voltage to the gate lines—this is one of the drive circuits for drive voltage application to the drive lines of a liquid crystal display device—along with an example of a printed wiring line layout as formed on a substrate. The gate drive circuit chip (simply referred to as “drive circuit chip” also hereinafter) GDR which is indicated by solid external shape lines or outlines has on its ventral surface a great number of input terminals IT and multiple output terminals OT along with dummy terminals DT, wherein this ventral surface is mounted onto a substrate with input wiring lines ITL and gate wiring lines GL formed thereon. The terminals of this type are also called bumps.
In this example, the input terminals IT are organized into two linear arrays disposed along the opposite peripheral edges—namely, the right and left side edges when seeing the attached drawing sheet of FIG. 7—of the drive circuit chip GDR. The input wiring lines ITL are formed on the substrate side in a way corresponding to the input terminals IT. Optionally, another example is available in which the input terminals IT are modified to reach up to the right and left ends of a lower peripheral edge of the drive circuit chip GDR. The output terminals OT for connection to the gate lines GL as formed in the display region placed at upper part of FIG. 7 are located at an upper peripheral edge of the drive circuit chip GDR, with the dummy terminals DT being formed along a lower peripheral edge thereof.
As shown in FIG. 10, a gate line GL which extends from the display region is connected to an output terminal OT that is formed on the drive circuit chip GDR and extends so that it runs beneath the ventral surface of the drive circuit chip GDR to reach a terminate end face of the substrate via a dummy terminal DT which is present at the lower peripheral edge. Note here that at an intermediate manufacturing stage of this display device, an electrical shortcircuiting or shorting line is provided at a portion which is further below the lower edge, wherein the above-noted gate line GL is connected to this shorting line. The short line is cut and removed away together with the substrate at a pre-stage at which it becomes a final product. This arrangement is shown in FIG. 9.
FIGS. 8A and 8B are partial views for explanation of the arrangement of a portion indicated by arrow “A” in FIG. 7. Additionally, FIG. 9 is a main-part plan view diagram for explanation of an arrangement example at the intermediate manufacture stage of the substrate which mounts thereon the drive circuit chip, and FIG. 10 is an explanation diagram of a connection state of either an output terminal or a dummy terminal of the drive circuit chip being mounted on the substrate with respect to a gate line. Reference character string “SUB1” designates the substrate (first substrate) used to mount the drive circuit chip; SUB2 indicates an opposite substrate (second substrate); PAD denotes power supply pads; CL is a cut line of the first substrate; SHT, electrical shorting line. The input wiring lines ITL are extended toward the power supply pads PAD as formed at a substrate end portion.
As shown in FIGS. 7 to 10, the dummy terminals DT on the lower peripheral edge side of the drive circuit chip GDR function to take a balance when mounting onto the substrate, together with the output terminals OT that are present on the upper peripheral edge side. The dummy terminals DT formed are the same in number as the output terminals OT, for taking a balance in the above-noted mounting event—more specifically, for preventing the drive circuit chip GDR from being mounted with a tilt. As shown in FIGS. 8A–8B, each gate line GL passes through a portion overlying the dummy terminal DT at the lower edge of the drive circuit chip GDR and is then connected to the shorting line SHT.
However, when providing the dummy terminals DT at the lower peripheral edge of the drive circuit chip GDR in units of respective gate lines GL, if these are formed in parallel to the aforesaid lower edge as shown in FIG. 8A, then a need is felt to expand the distance of respective gate lines GL in order to prevent unwanted contact between neighboring gate lines GL. As a result, the gate lines GL to be formed within a specified range D decrease in line number; thus, it is required to enlarge the size in a lateral direction along the lower edge of the drive circuit chip GDR.
Alternatively, as shown in FIG. 8B, when the dummy terminals are formed to have a zigzag shape at the lower peripheral edge of the drive circuit chip GDR while letting the gate lines GL that are formed within the specified range D be the same in number as the output terminals OT, it is necessary to enlarge an up-down direction size of the drive circuit chip GDR as indicated by an arrow.
In this way, with the prior art layout designs of the dummy terminals DT, there is a limit to the shrinkage of the outer shape of the drive circuit chip GDR. This means that it becomes difficult to reduce the area of the first substrate SUB1 which mounts thereon the drive circuit chip GDR and thus becomes one factor which constitutes a bar to miniaturization or “down-sizing” of the entirety of the display device.
It is therefore an object of the present invention to provide a display device capable of reducing the outer shape size of a drive circuit chip to be mounted on a substrate of the display device to thereby enable miniaturization as a whole.